A comprehensive study of scanner alignment mark quantity and layout-dependent effect for overlay performance optimization

In recent years, advances in semiconductor technologies have resulted in the continuous shrinkage of the process window required to fabricate a device, and specifically, the shrinkage of the overall overlay budget of the critical layers. Among other variables, a key contributor of wafer-to-wafer overlay variations is scanner alignment strategy. In high-volume manufacturing (HVM), the reduction in alignment mark count can lead to productivity improvement, however, that tradeoff impacts the scanner alignment layout and overlay model performance. In this paper, we present a comprehensive investigation of an in-line production experiment and simulation results to evaluate overlay performance by cooptimization of scanner alignment mark count, layout for High Order Wafer Alignment (HOWA) model.