Design of a CMOS 1.8V low voltage differential signaling receiver

The design of a 1.8V LVDS receiver operating at a maximum speed of 700Mbits/sec is presented. The receiver is designed to accept LVDS signals from 3.3V, 2.5V, or 1.8V systems and converts it to a 1.8V digital data. The design was completed on a 0.24/spl mu/m CMOS process and complying with the industry standard of /spl plusmn/10% power supply variations over a temperature range from -40/spl deg/C to +85/spl deg/C. At the nominal supply voltage of 1.8V and operating at maximum speed the receiver consumes less than 6.5mW.