SiC Fan-out Wafer Level Package for High Power Application

The thermal concept of the electronic package for high power devices needs to address the increased temperature of operation and the need to insure the head dissipation of the device. In common Fan-out packages Epoxy Mold compounds (EMC) are used which is not well adopted to high temperature operation as EMC has a low thermal conductivity. In this paper the research on the development of a Fan-Out Wafer Level Package is described. First a FEM simulation comparing a Mold compound and SiC Fan-out Packages was performed. It showed that the thermal resistance of the package can be reduced by 72% allowing up to 20 W/mm ² eight times power loss in a 3.9 mm ² package. Later a manufacturing process was developed for this SiC Fan-out Wafer level Package which suits for high power application addressing. For this package Wafer Level bonding techniques of SiC Wafers are used to embed the active chip, e.g. a Monolithic Microwave Integrated Circuit (MMIC). Through SiC Vias (TSiCV) are used to realize the backside contacts and a SiC nanoparticle filled adhesive is used to inprove the thermal conductivity of the bond interface.