Design of Dynamic Comparators using Tanner EDA Tools

A replacement absolutely differential CMOS dynamic comparator victimization feedback appropriate for pipeline A/D converters with low power dissipation, low offset, low noise and high speed is proposed. Inputs square measure reconfigured from typical differential try comparator specified close to equal current distribution within the input transistors may be achieved for a meta stable purpose of the comparator. Restricted signal swing clock for the tail current is additionally wont to guarantee constant currents within the differential pairs. Nearly 18mV offset voltage is definitely achieved with the proposed structure creating it favorable for flash and pipeline conversion applications.