Retention Characteristics of HfO 2 -based MFMIS FeFETs: Degradation Mechanism Revealed by Fast-PRER Measurement

Nonvolatile, low-voltage ferroelectric field-effect transistors (FeFETs) are promising for energy-efficient embedded storage in advanced logic and neuromorphic systems. The MFMIS FeFETs with a separated transistor fabricated by standard CMOS process and a gate-coupled ferroelectric capacitor have the advantages of ease of CMOS integration, performance optimization by tunning the area of 1T and 1C. However, the retention degradation of MFMIS FeFET is the issue for memory applications. In this work, we report a fast pulsed program-read-erase-read (PRER) measurement scheme on 1T-1C FeFETs showing that short (1 μs) post-pulse delays reveal substantially larger memory windows compared to DC readout. Delay-dependent measurement indicate that degradation retention loss is dominated by degradation in the program state, which is driven by channel-to-floating-gate electron tunneling and the resulting depolarization field, whereas the erase state remains stable within 10 ms. These findings clarify retention mechanisms and suggest pulse-optimized operation for improved nonvolatile performance.