Tailored Local Dielectrics via Area-Selective ALD for Co-Optimizing Performance and Reliability in 3D NAND Flash Memory

Abstract We present a material-level strategy for co-optimizing the performance-reliability trade-off in 3D NAND flash memory via selective spacer expansion (SSE) enabled by area-selective atomic layer deposition (AS-ALD). A 3D NAND technology computer-aided design (TCAD) framework, calibrated against measured incremental step pulse programming (ISPP) and retention characteristics, is established to quantify how spacer thickness and dielectric constant modulate program efficiency, word-line (WL) interference, and retention without altering the baseline cell geometry. Three representative spacer materials, SiO2 (ϵ = 3.9), SiOC (ϵ = 2.7), and SiCOH (ϵ = 2.2), along with an idealized low-k limit (ϵ = 1.0) as a theoretical bound, are evaluated to construct a material-dependent spacer design map. In addition, a low-k spacer (ϵ = 1.0) is idealized as a theoretical bound. Our findings demonstrate that SiO2 spacers enhance program efficiency by up to 24.9% at a spacer thickness of 7 nm through curvature-induced electric-field concentration near the tunneling oxide (Tox). At an 8 nm spacer thickness, SiO2 spacers also suppress WL interference and retention loss by 28 and 20.5%, respectively, by mitigating edge electric-field crowding and lateral charge migration. By comparison, SiCOH spacers increase program efficiency by 13.1% at 7 nm and reduce WL interference and retention loss by 32.3 and 34.2%, respectively, at 8 nm. The intermediate behavior of SiOC spacers indicates that a moderate dielectric constant provides a practical design window for balancing program acceleration and reliability improvement, highlighting spacer geometry as an effective electrostatic control knob. In the examined design space, an optimal spacer thickness of 7–8 nm achieves balanced performance and reliability across the evaluated materials. Furthermore, the optimal spacer thickness decreases with metal-gate scaling, indicating improved process feasibility through a reduced required AS-ALD spacer thickness. These findings establish dielectric spacer engineering as an effective material-level design knob for performance-reliability co-optimization in future high-stack and multi-level-cell 3D NAND flash memory.