The special trench design near the through silicon vias (TSVs) to reduce the keep-out zone for application in three-dimensional integral circuits

Trench structure is designed and used to release process induced stress, resulting from the different material thermal expansion coefficients, in three-dimensional integral circuits (3DICs). The stress in the designed trench structure is measured by atomic force microscope Raman technique experimentally, and simulated by the full process simulation model. With the help of this simulation model, the optimized trench structure near the copper-filled TSV is designed and reported. The experimental data demonstrate that the tensile stress near the TSV can be reduced from 600 MPa to 150 MPa and the corresponding keep-out zone (KOZ) can also be decreased ∼4 times with the designed trench structure having a depth of 10 µm and spacing distance of 8 µm to the TSV. This work provides one potential solution to release process induced stress for real application of 3DICs.