Investigation of Low Temperature SiP Epitaxy on 300 mm Si Substrate

To continue the scaling down of transistors several challenges needs to be addressed, including the contact resistivity at the interface of the contact metal and the source/drain (SD) region, and the source/drain bulk resistivity. Phosphorous doped Si (Si:P) is commonly used for nFET as an alternative for (Si:C):P. In this work we report on low temperature (LT) epitaxy (below 500℃) of Si:P layers with extremely low as-grown layer resistivity. Optimal growth conditions at 400℃ led to a layer resistivity of 0.2 mOhm.cm and an active dopant concentration of ~1.15×10 21 cm -3 . Finally, the as-grown layer properties are compared to existing literature data. SiP layers were grown in a 300 mm ASM Intrepid ® ES reduced pressure chemical vapor deposition reactor on Si(001) substrates. The Intrepid ® system is equipped with a Previum ® module for pre-epi cleaning at low temperatures. First, a set of Si:P layers was epitaxially grown at 470°C, with various Si precursor flows. The pressure, carrier flow and PH 3 flow were kept constant. Figure 1 shows the omega-2theta scans around the symmetric (004) reflections of the Si:P/Si stacks. As expected, reducing the Si precursor flow leads to a higher substitutional P incorporation in the layer. The Si:P layer is pseudomorphic with good crystalline quality, as indicated by the thickness fringes. Figure 2 summarizes the HR-XRD angular spacing versus the SIMS content from different literature papers [1-4]. We note that for a low P doping level (<4%) the data are almost overlapping, while the spread increases for a high P content. This could be attributed different SIMS calibration for high P content. Using these calibration curves we note that the P content in the layers shown in Fig. 1 varies between ~1% to around 8.5% ± 0.5%. Figure 3 represents the resistivity versus the P content at three different temperatures (470°C, 440°C and 400°C). Definitely, the growth conditions were tuned to enable a growth with an acceptable growth rate at 400°C. The results indicate that reducing the growth temperature leads to a reduction in the layer resistivity, for the same P content. This highlights that the well-known P deactivation mechanism is correlated to the growth temperature. Figure 4 reveals AFM scans for the Si:P layers with different P content showing that smooth surface morphology can be obtained. Figure 5 compares the (micro-) Hall mobility versus the active concentration for the Si:P process developed in this frame work at LT to data obtained for DCS based process at high temperature (HT) (at 670°C). The DCS based layers were subjected to different thermal anneals [1]. The LT Si:P process follows the same trend, i.e. the Hall mobility decreases when the active dopant concentration increases. The reduction could be attributed to an increase in ionized impurity scattering. This explains the resistivity value around 0.2 mOhm.cm regardless of the P content at 400°C. Figure 6 shows the active dopant concentration as a function of the total dopant concentration. The LT process significantly outperforms the HT process in terms of ratio of active dopant over total dopant concentration. Furthermore, it shows an improvement in active dopant concentration even when compared to the layers exposed to ms laser anneal. Figure 7 summarizes the resistivity value for a Si:P layer obtained at high temperature and subsequently subjected to different anneals and the Si:P layer grown at 400°C, with a P content around 3%. Figure 8 shows the smooth surface morphology of the LT SiP layer with a resistivity of 0.2 mOhm.cm. Finally, Table 1 summarizes the key parameters for the Si:P layers found in literature and compare it to this work. To conclude, LT Si:P epitaxy paves the road towards new applications and is required for novel device architecture. However, a selective process is at utmost importance for integration schemes, which is currently under investigation. [1] E. Rosseel et al, ECS Trans. 75 (8) (2016) 347. [2] K.D Weeks et al, Thin Solid Films 520 (2012) 3158. [3] M. Lee et al, ACS Appl. Electron. Mater. 1 (3) (2019) 288. [4] X. Li et al, ECS Trans. 64 (6) (2014) 959. [5] J.M. Hartmann et al, Semicond. Sci. Technol. 32 (2017) 104003. [6] C.N. Ni et al, VLSI Technology, Kyoto, (2015) T118-T119. [7] M. Bauer el al, ECS Trans. 33 (6) (2010) 629. [8] Z. Ye et al, ECS Trans. 50 (9) (2012) 1007. Figure 1