Source/Drain Epitaxy and Contacts for CFET Applications

Transistor miniaturization has for a long period of time enabled the so-called ‘happy scaling era'. Scaling devices made them faster, cheaper and more energy efficient. Despite a slowdown of this trend in the 2000s, the introduction of strained channels, high-k / metal gates and non-planar field-effect transistors successfully extended the famous Moore's law. In the meantime, parasitic contributions from access resistances became important performance detractors [1]. Active doping concentrations in SiGe:B and Si:P epitaxial layers, typically used as source/drain (S/D) materials in PMOS and NMOS transistors, respectively, should hence be maximized to reduce contact resistivities (pc) [2]. Engineering the band structures in the contact regions and identifying suitable contact metals and silicides, enabling advantageous replacements of Ti silicides, are other subjects of intense research efforts.