宏
电阻随机存取存储器
计算机科学
乘法(音乐)
特拉-
缩放比例
矩阵乘法
并行计算
半导体存储器
GSM演进的增强数据速率
计算科学
计算机工程
计算机硬件
电子工程
电气工程
电压
人工智能
工程类
数学
物理
程序设计语言
组合数学
操作系统
量子
量子力学
几何学
作者
Qiang Huo,Yang Yi-ming,Yiming Wang,Dengyun Lei,Xiangqu Fu,Qirui Ren,Xiaoxin Xu,Qing Luo,Guozhong Xing,Chengying Chen,Xin Si,Hao Wu,Yiyang Yuan,Qiang Li,Xiaoran Li,Xinghua Wang,Meng‐Fan Chang,Feng Zhang,Ming Liu
标识
DOI:10.1038/s41928-022-00795-x
摘要
Abstract Non-volatile computing-in-memory macros that are based on two-dimensional arrays of memristors are of use in the development of artificial intelligence edge devices. Scaling such systems to three-dimensional arrays could provide higher parallelism, capacity and density for the necessary vector–matrix multiplication operations. However, scaling to three dimensions is challenging due to manufacturing and device variability issues. Here we report a two-kilobit non-volatile computing-in-memory macro that is based on a three-dimensional vertical resistive random-access memory fabricated using a 55 nm complementary metal–oxide–semiconductor process. Our macro can perform 3D vector–matrix multiplication operations with an energy efficiency of 8.32 tera-operations per second per watt when the input, weight and output data are 8, 9 and 22 bits, respectively, and the bit density is 58.2 bit µm –2 . We show that the macro offers more accurate brain MRI edge detection and improved inference accuracy on the CIFAR-10 dataset than conventional methods.
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