Design and Process Analysis of a Split-Gate Trench Power MOSFET With Bottom-Trench High-k Pillar Superjunction for Enhanced Performance

In this paper, we propose a simulation-based novel Split-Gate Trench MOSFET structure with an optimized fabrication process to enhance power efficiency, switching speed, and thermal stability for high-performance semiconductor applications. Integrating High-k pillars Superjunction beneath the Split-Gate enhancing breakdown performance by reducing critical field intensity by up to 35%, the device achieves a 15% improvement in Figures of Merit (FOMs) for $\mathrm {BV}^{2}/R_{\mathrm {on,sp}}$ . Dynamic testing reveals approximately a 25% reduction in both input and output capacitance, as well as gate-drain charge ( $Q_{\text {GD}}$ ). This reduction, coupled with an approximately 40% improvement in Baliga’s High-Frequency Figure of Merit (BHFFOM) and over 20% increase in the New High-Frequency Figure of Merit (NHFFOM), underscores the design’s suitability for high-speed, high-efficiency power electronics. Simulations examining the effects of High-k pillar depth indicate that an optimal depth of $3.5 \; \mu $ m achieves a balanced performance between BV and $R_{\text {on,sp}}$ . The influence of High-k materials on BT-Hk-SJ MOSFET performance was investigated by comparing hafnium dioxide (HfO2), nitride, and oxynitride. Among these, HfO2 demonstrated optimal performance across static, dynamic, and diode characteristics due to its high dielectric constant, while material choice had minimal impact, with variations kept within 5%.