Evolution Kinetics of Voids in Electroplated Cu-Cu Wafer Bonding

Cu-to-Cu direct bonding implemented in three-dimensional (3D) integrated circuits (ICs) has been widely studied. Formation of interfacial voids occurs in the absence of atomically smooth surfaces when wafers are mated together at room temperature. At elevated temperature, interfacial voids undermine the reliability of devices. Cu-Cu bonding usually accompanies oxide-oxide bonding to form hybrid bonding. Compressive stress can occur at Cu-Cu bonded interface. This study introduces artificial voids at bonded interfaces by bonding an etched Cu sample to an unetched Cu sample. The evolution and the healing kinetics of interfacial voids at temperatures from 120 °C to 250 °C were examined. Results revealed no sample bonding at temperatures below 120 °C (B120) and that healing of samples B150, B200 and B250 occurred only with compressive stress.