跨导
材料科学
晶体管
光电子学
纳米线
泄漏(经济)
阈值电压
栅氧化层
场效应晶体管
电气工程
电压
工程类
宏观经济学
经济
作者
Akhil S. Kumar,Swaroop Ganguly,Dipankar Saha
标识
DOI:10.1002/pssr.202200100
摘要
Lateral nanowire (NW) field‐effect transistors are fabricated by a top‐down approach on an AlGaN/GaN heterostructure. A combination of dry and anisotropic wet etching is used to form the NW. The channel is controlled by a 2D electric field originating from two partial gates on the parallel sides of the nanowire channel. While a larger overlap of the gate with the channel region, as in a gate‐all‐around transistor, improves gate control in terms of transconductance gm, gate leakage current and I ON / I OFF deteriorate. Partial overlapping gate transistors are found to provide a trade‐off, providing extremely low gate leakage current (≈10 μA cm −2 ), very low I OFF (100 fA μm −1 ), and very high I ON / I OFF (5 × 10 8 ). Despite the nature of the partial gate, a good subthreshold swing (SS) of ≈79 mV decade −1 is observed. Various transistor performance parameters can be tuned within a certain window of trade‐offs between them as the transistor evolves from a partial gate to a gate‐all‐around structure. A 1D nature of the channel near the transistor threshold voltage is found to offset the limitations of the partial gate.
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