加法器
功率延迟产品
计算机科学
电子线路
传播延迟
晶体管
功率(物理)
串行二进制加法器
电子工程
进位保存加法器
碳纳米管场效应晶体管
计算
电压
电气工程
场效应晶体管
CMOS芯片
工程类
算法
物理
量子力学
作者
Bhargav Avireni,Phat Huynh
出处
期刊:Sensors
[Multidisciplinary Digital Publishing Institute]
日期:2021-12-08
卷期号:21 (24): 8203-8203
被引量:7
摘要
Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.
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