P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors

We have demonstrated a complementary metal-oxide-semiconductor inverter logic gate by heterogeneous integration of an enhancement-mode n-channel transistor on GaN and a p-channel transistor on diamond. A thermally grown p-type NiOx is used as the dielectric, and Ni/Au is the gate metal for both transistors. NiOx oxide on top of a partially recessed-gate AlGaN/GaN heterostructure depletes the two-dimensional electron gas by pulling the Fermi level closer to the valence band and making it normally OFF. The combination of Ni/NiOx gate metal work function and the dielectric helps to deplete the two-dimensional hole gas channel of a hydrogen-terminated p-channel diamond, making it an enhancement mode. The GaN n-MOS and diamond p-MOS transistors show output and transfer characteristics with threshold voltages of +0.6 and −1.2 V, respectively. nMOS and pMOS transistors show ION/IOFF current ratios of >105 and >103, respectively, with a subthreshold leakage of <10 μA/mm. The gate current is negligible for both devices. The saturation drain current of the respective transistors is measured to be ∼170 and ∼20 mA/mm at a gate-to-source overdrive voltage of 3 V. The inverter input–output characteristics and transient response are measured for various rail-to-rail voltages and frequencies. The inverter threshold voltage is measured to be 1.1 V for a nominal operating voltage of 3 V.