材料科学
锗
场效应晶体管
光电子学
蚀刻(微加工)
金属浇口
钝化
晶体管
纳米线
纳米技术
各向同性腐蚀
图层(电子)
硅
栅氧化层
电气工程
电压
工程类
作者
Lu Xie,Huilong Zhu,Yongkui Zhang,Xuezheng Ai,Junjie Li,Guilei Wang,Jinbiao Liu,Anyan Du,Hong Yang,Xiaogen Yin,Weixing Huang,Chen Li,Yangyang Li,Qi Wang,Shunshun Lu,Zhenzhen Kong,Jinjuan Xiang,Yong Du,Jun Luo,Junfeng Li
出处
期刊:ACS Nano
[American Chemical Society]
日期:2023-10-12
卷期号:17 (22): 22259-22267
被引量:5
标识
DOI:10.1021/acsnano.3c02518
摘要
A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of ∼291 μA/μm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.
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