Sustainable semiconductor manufacturing: lessons for lithography and etch

Sustainability is gaining momentum as countries and companies announce targets for net-zero carbon emissions by 2050. imec has created a bottom-up model using tool data, process recipes, and integrated wafer process flows to create a virtual fab. With this model, it is possible to quantify the environmental impact of manufacturing integrated circuit (IC) chips for current and future logic and memory technology modes. In this paper, the model is used to identify areas with the highest environmental impact. It is important to reduce the impact of both lithography and etch since together they are responsible for 45% of total CO₂ equivalent emissions associated with fabricating an N3 logic node wafer. For lithography, two approaches to reducing the environmental impact will be described: one concentrates on tool consumption and the other on process choices to maximize throughput. For etch, the focus is on reducing overall gas consumption and improving wafer material stacks to minimize fluorocarbon use. Translating patterning process changes into emission numbers will enable informed process choices for future and contribute to a shift towards net-zero semiconductor manufacturing.