A Floating‐Gate Photoelectric Synaptic Transistor Utilizing BP/PO x /WSe 2 Heterostructure for Neuromorphic Visual Processing

Abstract Artificial intelligence (AI) is constrained by the high energy consumption of von Neumann architectures and the limited scalability of traditional silicon‐based synapses. Two‐dimensional (2D) van der Waals (vdW) materials, with their atomic‐scale thickness, tunable electronic properties, and ease of heterogeneous integration, offer a promising platform for next‐generation neuromorphic hardware. Here, the authors report a vdW floating‐gate transistor (BP/PO x /WSe 2 ) with a high on‐off current ratio (≈10 5 ) and a large memory window (73 V), benefitting from the optimized interface band alignment via 2D heterostructure engineering. Key synaptic functionalities are demonstrated, including short‐term plasticity (STP), long‐term plasticity (LTP), and electro‐optical dependent plasticity, short‐term paired‐pulse facilitation (PPF), and long‐term potentiation/depression (LTP/D). Notably, the device mimics human visual memory under optical stimuli while achieving ultralow energy consumption (10 pJ per synaptic event), outperforming most reported photoelectronic synaptic devices. Furthermore, a two‐path convolutional neural network (CNN) is introduced that synergistically merges optical and electronic inputs, which enables efficient feature extraction and weight updating, and achieves 96.9% accuracy in the Labeled Faces in the Wild (LFW) face recognition task. The work presents a promising approach for neuromorphic electronics, paving the way for energy‐efficient vision processing in edge AI applications.