A One‐Transistor Logic Gate with 50% Smaller Footprint by Foundry Process and Beyond

Abstract Logic gates are the fundamental components of integrated circuits (ICs). However, modern logic gates that have over one transistor encounter scaling‐down issues; most presently emerging logic gate structures with advanced materials generally could not be compatible with the foundry lines or also need more than one transistor to provide a voltage output. Here, a multifunctional multi‐terminal zero‐additional‐resistor‐process one‐transistor with the novel channel electrode design architecture (MZT) compatible with foundry lines, which alone provides a voltage output, and implement logic gates, memory, sensing and artificial synaptic behaviors, is proposed. MZT is compatible with all fabircation processes, including top‐gate processes, foundry line processes and bottom‐gate processes. It could reduce the footprint of logic NOT by 50%. It could have a memory retention time over 20 min, and its array has low half‐select disturbance. MZT exhibits artificial synaptic behaviors, with a power dissipation as low as the brain per synaptic event. MZT is proved to be fabricated by the foundry repeatedly. In the light of this, the MZT arrays demonstrate the controllable visualization recognition probability with convolutional neural networks (CNN) and faster reading speed than static random access memory (SRAM) based on simulation. MZT provides a promising strategy for many and future ICs.