A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems

The growing demand for big data and cloud computing requires high-speed, high-capacity storage systems. While the speed of host interfaces (IFs), such as the PCIe employed in SSDs, is steadily increasing, it is becoming more difficult to increase the IF speed of NAND Flash Memory (NAND). This is partly because signal integrity is severely degraded when a high-capacity SSD requires multiple packages with multi-stacked NAND dies on each PCB channel, and partly because the increased number of word line stack layers and multi-levels (3b/cell or 4b/cell [1]) of NAND tend to increase the NAND read latency (tR). If the tR exceeds the data output period, the read throughput is limited by the tR. Thus, only increasing the speed of the NAND IF does not produce higher throughput. To reduce the tR, a single-level cell and higher multi-plane architecture, such as 16 instead of 2 or 4, are employed [2]. This architecture inflates the system cost. It has been reported that reducing the channel load by using an LSI IF between the SSD controller (Controller) and NAND [3] is one method to increase the SSD capacity. However, it does not provide speed beyond that of the NAND IF and still requires an increasing the number of NAND IF channels on the PCB in accordance with advancing PCIe development.