锁相环
CMOS芯片
电气工程
计算机科学
压控振荡器
电子工程
频率合成器
相位噪声
分频器
功率(物理)
dBc公司
无线电频率
时钟发生器
抖动
相位频率检测器
电压
作者
Xiang Gao,Luns Tee,Wanghua Wu,Kun-Seok Lee,Arvind Anumula Paramanandam,Anuranjan Jha,Norman Liu,Edwin Chan,Li Lin
出处
期刊:International Solid-State Circuits Conference
日期:2015-03-19
卷期号:: 1-3
被引量:27
标识
DOI:10.1109/isscc.2015.7062978
摘要
The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver good EVM performance. On the other hand, smaller area and lower power are always desired for lower cost and longer battery life. This work presents a 28nm CMOS LO design for dual-band 802.11abgn/ac radio with overall architecture shown in Fig. 9.4.1. It addresses the aforementioned challenges with a low-noise integrated XTAL oscillator, a fractional-N digital PLL utilizing 1) background reference clock-doubler duty-cycle error correction and quantization noise cancellation, 2) non-periodic DCO dithering and compensation, and an offset LO frequency plan based on a self-mixing frequency tripler. The PLL design achieves 0.36° integrated phase error or 0.17ps rms jitter while consuming 9.5mW, leading to a record FOM of −245.5dBforfrac-N PLLs.
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