饱和速度
晶体管
速度饱和
饱和(图论)
电场
晶体管型号
场效应晶体管
物理
材料科学
电气工程
光电子学
电压
工程类
MOSFET
数学
量子力学
组合数学
作者
J. Paredes,S. Hidalgo,F. Berta,Juan Manuel Fernández,J. Rebollo,José del R. Millán
摘要
An analytical model is proposed in order to explain the DC VDMOS transistor performance. It accounts for the device linear region, and the quasi-saturation effect is included in the formulation by considering the carrier velocity saturation at high electric field values. Electric field and majority-carrier distributions can be deduced from the model which agree with the results obtained from two-dimensional simulations. This formulation predicts a majority-carrier excess inside the epilayer even before the carrier velocity saturation is achieved. Interdigitated VDMOS transistors have been fabricated and two-dimensional simulations have been carried out in order to check the output characteristics against the proposed model.< >
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