Design Considerations for High Performance Vertical Channel DRAM Cell Array Transistor

This paper address challenges in designing next generation $\mathbf{4 F}^{\mathbf{2}}$ DRAM cell array transistor. A comprehensive study was conducted on the junction extension coupling effects on the device characteristics of cell array transistors having ultrathin body. Dual work function word line and raised back gate as a junction extension shield were introduced as the most feasible solutions to cope with the junction extension coupling effects. Performance gain by these architectures allows the junction extension to be designed in a way more resistant to the coupling effects.