A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters

A 12-bit 104 MS/s successive approximation register analog-to-digital converter (SAR ADC) is developed for a digitally-assisted wireless transmitter system for use in cellular applications. A power-on calibration method is implemented to correct capacitor DAC mismatch and reduce capacitor size, thereby lowering the current consumption of the input buffer and reference generator. The total capacitor size is reduced to 0.6 pF, from the 3.6 pF required for 12-bit matching. The ADC analog core area is 0.003 mm ² . The proposed method achieves 88 dB SFDR at 26 MHz sampling rate and 76.2 dB SFDR at 104 MHz sampling rate after calibration. The measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The ADC achieves both high speed and low power by combining several features, namely digital calibration, redundancy, asynchronous bit-cycling, monotonic switching, 25% duty-cycle sampling period, 3 dB input gain, and a fully dynamic comparator. The power consumption from 1.2 V/1.1 V supplies is 0.88 mW for a single ADC core and 6.1 mW for the entire I/Q ADC, including the reference generator and input buffers. The ADC is fabricated in 28 nm CMOS.