Live demonstration: Hardware-software co-verification for very large scale SoC using synopsys HAPS platform

This demo presents the verification framework for very large scale SoC System using Synopsys HAPS platform. The IEEE 802.1 lac WLAN system is selected as a case study for verification purpose. The HW/SW co-verification is carried out to confirm the feasibility of proposed system, to test data flow, and to early verify HW-SW integration. Some user experiences are also offered by proposed system such as easy controlling and fast system performance evaluation. The implementation results show that the design occupy 65,459 LUTs, 39,957 registers and 428 block RAMs, which are about 18% of available total slices in one FPGA chip. The very large SoC that utilizes up to 20 times of proposed design (equivalent to 30 Mgate) can fit into all FPGA chips inside HAPS platform.