New Silicon Capacitor Solutions with Over 1mm - Thick Core Based Embedded Substrate for Extremely Large Package Platform

Due to the increasing demand for Artificial Intelligence (AI) technology and technological advancements, there is an industry trend of integrating multiple dies, including High Bandwidth Memory (HBM) and Dynamic Random Access Memory (DRAM), resulting in larger package sizes. As the package size increases, the substrate size becomes larger and thicker, making it difficult to use embedded capacitor solutions on the substrate. Typically, package designs that use Die Side Capacitor (DSC) are mounted on side by die. In this paper, the authors propose two embedding silicon capacitor solutions that can be used in extremely large packages with core thicknesses exceeding 1 mm to address these issues. [1] Firstly, the authors propose a silicon capacitor solution with dummy silicon attached. Due to the thickness of the silicon wafer used in Deep Trench Capacitor (DTC) is limited, it is not possible to manufacture the silicon capacitor with thickness exceeding 780 um. Therefore, the silicon capacitor is fabricated as a wafer, and then Die Attach Film (DAF) is attached to the rear side of the silicon capacitor wafer. To achieve the required thickness, the dummy wafer is then attached on top of the DAF. In contrast to conventional silicon capacitors, this method can achieve a thickness of more than 1 mm. Secondly, the authors propose Side Stacked Silicon Capacitor (SSSC) solution, in which multiple layers of silicon capacitor wafers are stacked and mounted laterally on core based substrate. The first layer begins with a dummy wafer, followed by subsequent layers of silicon capacitor wafer. The wafers are bonded using Non-Conductive Film (NCF), and copper bumps with a thickness of more than 50 um are used for electrical connection. To prevent cracks in silicon layers due to its thinness, a molding material is formed in the center of SSSC. The SSSC design offers the advantage of high capacitance and enables double sided connections, maximizing the effectiveness of package Power Delivery Network (PDN) connections. The silicon capacitor solutions proposed by the authors are applicable as embedded Capacitor (eCAP) solutions in extremely large package designs with core thicknesses exceeding 1 mm, such as those used in AI, High Performance Computing (HPC), automotive applications. These solutions contribute to improving System on Chip (SoC) performance by enhancing impedance characteristics and voltage stability. This paper presents a comparative simulation study of PDN performance when utilizing capacitor solutions as DSC and eCAP components in extremely large package designs. Power Integrity (PI)-based simulation results focus on impedance characteristics and voltage drop outcomes. In this experiment, an actual automotive SoC using a thick core substrate based package platform is evaluated.