Simulation and Design of the 3D Silicon Capacitor Structure Charactered by Low-Parasitic, High-Capacitance and High-Reliability

Three-Dimensional Bilayer Silicon Capacitor: Electrical Characteristics, Parasitic Effects, and Thermal Reliability Analysis. Silicon-based capacitors have emerged as a research focus in high-frequency circuits due to their high integration density and excellent reliability. However, under high-frequency operation, parasitic effects such as equivalent series resistance (ESR), equivalent series inductance (ESL), and thermal stability remain key challenges limiting their performance. Therefore, an in-depth study of the electrical characteristics and reliability of silicon capacitors is essential for optimizing capacitor design. This paper establishes a 3D bilayer silicon capacitor model and conducts systematic research in three aspects. First, the C-V characteristics of a MOS capacitor are simulated using Sentaurus TCAD. A DC sweep is employed to obtain the steady-state potential distribution, while AC small-signal analysis is applied to compute the high-frequency C-V curve. By solving the Poisson equation and carrier transport equations, the C-V variations in accumulation, depletion, and inversion regions are investigated. The simulation results reveal significant nonlinear behavior in the C-V characteristics under varying gate voltages. Under negative gate bias, the device operates in accumulation mode, with capacitance approaching the oxide capacitance. As the gate voltage increases, the device enters the depletion region, where the capacitance behaves as a series combination of oxide and depletion capacitances. At higher gate voltages in the inversion region, the capacitance at low frequencies recovers to the oxide capacitance, whereas under high-frequency conditions, it stabilizes at the depletion capacitance due to limited minority carrier response. Second, the ESR and ESL characteristics of the bilayer silicon capacitor are analyzed using ANSYS HFSS electromagnetic simulation. A 3D full-wave electromagnetic model is constructed, incorporating conductor losses, dielectric losses, and the impact of the 3D stacked structure on parasitic parameters, to accurately extract ESR and ESL in the 1 MHz to 10 GHz range. Frequency-dependent material parameters and adaptive mesh refinement techniques ensure the accuracy of high-frequency resonance analysis. The simulations demonstrate that ESR is primarily dominated by dielectric loss at low frequencies (<100 MHz), while ESL is significantly influenced by the magnetic field distribution of the 3D interconnect structure at high frequencies (>1 GHz). A comparison with TCAD simulation data shows an error margin within 5%, validating the model’s reliability. This study provides a theoretical foundation for the optimized design of 3D silicon capacitors with high-frequency low-parasitic performance, large capacitance density, and high mechanical reliability.