A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process

This work presents a high-resolution programmable frequency divider to select the frequencies that will be generated in DCO (Digitally Controlled Oscillator) or VCO (Voltage Controlled Oscillator) that will benefit the design of high-speed, wide-range PLL for Internet-of-Things (IoT) applications. The design is verified through post-layout simulations at 1 GHz input clock. The design achieves a division ratio range of 2-2048 with minimum and maximum operating frequencies of 488 KHz and 500 MHz, respectively. This work is carried out using 40-nm CMOS technology at 60 pF capacitive load and an average power consumption in worst case post layout simulation is 0.470 mW at 500 MHz.