Modeling and characterization of low frequency noise in self-aligned top-gate coplanar IGZO thin-film transistors

Abstract A modified low-frequency noise (LFN) model was proposed to accurately estimate the quality of the gate dielectric in self-aligned top-gate (SA TG) coplanar structure indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs). The proposed LFN model was derived by modifying the conventional carrier number with correlated mobility fluctuation model considering the peculiar characteristics of SA TG coplanar IGZO TFTs such as the channel length reduction due to the diffusion of hydrogen atoms or oxygen vacancies from the source/drain to the channel, as well as the relatively large source/drain parasitic resistance. The proposed model was validated by demonstrating that the measured LFN values were in good agreement with the predicted values from the proposed model for all SA TG coplanar IGZO TFTs with SiO 2 gate dielectrics deposited under different plasma-enhanced chemical vapor deposition (PECVD) power densities. The near-interface gate dielectric trap densities extracted from each TFT using the proposed LFN model revealed a clear increase as the PECVD power increased, which is considered a major cause of poor positive-bias-temperature-stress stability of the SA TG coplanar IGZO TFT with SiO 2 gate dielectric deposited under high PECVD power conditions.