A mm-Wave Concurrent Dual-Band Dual-Beam Phased Array Receiver Front-End in 22-nm CMOS FDSOI

This article presents a mm-Wave concurrent dual-band (28 and 39 GHz) dual-beam phased array multiple-input multiple-output (MIMO) receiver (RX) front-end with mid-band rejection in the 22-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. This phased array RX front-end has four inputs and two output streams with fully connected (FC) configuration where it takes advantage of sharing low-noise amplifier (LNA) and quadrature network (QN) and using a unique phase shifter (PS) structure which allows power and area saving. The measured 3-dB gain bandwidth is from 23 to 30 GHz for the lower bandwidth with a peak gain of 21 dB at 29 GHz, and from 36 to 40 GHz for the upper bandwidth with a peak gain of 18 dB at 38.5 GHz, and a noise figure (NF) of a minimum of 6 and 7 dB at 28 and 37 GHz, respectively. The 21-dB mid-band rejection at 33.5 GHz is provided by the LNA to attenuate the out-of-band unwanted interference helping relaxing the linearity requirement. The entire single-channel RX front-end achieves third order intercept point (IIP3) varying from $-$ 18 to $-$ 11 dBm, and input 1-dB compression point varying from $-$ 25 to $-$ 18 dBm. The front-end has 5-bit phase control and 7-dB gain control achieving the rms phase and gain errors less than 6 $^\circ$ and 1.2 dB, respectively, enabling orthogonality. This array demonstrates the concurrent functionality and carrier aggregation (CA) for over-the-air (OTA) beam-steering and error vector magnitude (EVM) measurements. The chip has a length of 2738 $ \mu$ m, a width of 1808 $ \mu $ m, and an area of 4.95 $ \text{mm}^2 $ including all dc, radio frequency (RF) pads, and decoupling capacitors.