模具(集成电路)
材料科学
薄脆饼
倒装芯片
互连
三维集成电路
堆积
晶片键合
成套系统
光电子学
集成电路封装
热压连接
电子工程
集成电路
电气工程
纳米技术
图层(电子)
炸薯条
计算机科学
工程类
胶粘剂
物理
核磁共振
计算机网络
作者
Guanghai Gao,Laura Mirkarimi,G. G. Fountain,Dominik Suwito,Jeremy A. Theil,Thomas Workman,Cyprian Uzoh,Gabe Guevara,Bongsub Lee,Michael Huyhn,P. Mrozek
标识
DOI:10.1109/ectc32696.2021.00071
摘要
The direct bond interconnect (DBI®) technology is a platform technology that offers a hermetically sealed hybrid bond with solid metal-metal (Cu-Cu is the most common) interconnect at a relatively low thermal budget. The Xperi wafer to wafer hybrid bonding technology has been in high volume production since 2015. The Xperi die to wafer hybrid bonding technology, DBI® Ultra, is now ready for industry adoption and ramp to manufacturing. The bond takes place at room temperature in an ambient environment in a class 1000 cleanroom; therefore, offers bond throughput comparable to mass reflow flip chip assembly. A low temperature batch anneal after bonding results in a solid Cu-Cu connection surrounded by dielectric for improved thermal performance. The value of the hybrid bonded Cu-Cu technology may be realized at various interconnect pitches for different applications. For die to wafer and die to die application with through silicon vias (TSVs), significant performance and cost advantages can be achieved at sub-40um pitch through elimination of both the solder and underfill materials from the package. Additionally, the technology may be scaled to sub-micron interconnects to enable widespread disaggregation and chiplet architecture innovation. Xperi's development efforts target the sub-40um pitch die-to-wafer stacking, which can be enabled with the existing Si supply chain. Previously, we have reported assembly results with daisy chain die in single layer and in die-to-wafer stacking with or without TSVs. In this paper, we report on a 5-die stack hybrid bonded module with TSV and the latest fabrication, assembly process, electrical testing and reliability performance. The reliability tests include autoclave, high temperature storage and temperature cycling with pre-conditioning at MSL3 per JEDEC specification.
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