The Study of TSV-Induced and Strained Silicon-Enhanced Stress in 3D-IC

In this work, we discuss the influences of strained silicon technology on transistors in the context of TSV thermal stress. An accurate thermal stress distribution around a single TSV is firstly obtained by finite element analysis. Then we simulate the transistors using strained silicon technology and apply the TSV stress to the structure to study their magnitudes and mutual influences. It is demonstrated that the stress distribution combination of these two stress sources of planar transistors can be viewed as the superposition of the separate results. Finally, based on the updated stress distribution, the mobility variations of transistors around the TSV are studied.