A Single-Layer Mechanical Debonding Adhesive for Advanced Wafer-Level Packaging

Better performance and lower cost are always key trends being pursued in the semiconductor industry. Moore's law has provided a very well-defined relationship between performance and cost and the semiconductor industry has followed this law for the past several decades with no issue. However, it became more and more difficult for foundries and integrated device manufacturers (IDMs) to scale to the next technology node without significant increase on the cost of ownership due to tremendous investment. As a result, advanced wafer-level packaging technologies have attracted significant amounts of attention because they have been demonstrated that the performance of a final device can be remarkably improved in a more cost-effective way. Therefore, there will be more demand for new and innovative packaging materials in order to enable these advanced packaging technologies. In this paper, a single-layer mechanical debonding adhesive is presented. The current temporary bonding and debonding solutions mostly focus on two- or three-layer materials, consisting of a bonding layer, a releasing layer, and even an adhesion promotion layer as needed, which greatly increases the cost of ownership and deteriorates throughput by requiring multiple coating and baking processes. Alternatively, the material presented in this work can provide several advantages over other material systems, such as 1) ultrathin wafer handling; 2) high thermal stability; 3) low warpage for high-stress substrates; 4) single coating and baking to reduce cost of ownership and improve throughput; 5) simple material cleaning. It has been demonstrated that the bonded wafer pair can be thinned down to 20 μm on blank silicon wafers with no defects or edge chipping and was able to pass 250°C during a 30-minute thermal simulation due to its high thermal stability (> 300°C). In addition, the wafer pair was successfully debonded on the commercial mechanical debonder. Furthermore, the material presents very low warpage (<; 30 μm on 8" wafer) for the bonded wafer pair, which shows great potential to handle substrates with high stress such as epoxy compound wafers and SiC/GaN wafers. Therefore, wafer cleaning, throughput, and material cost of ownership can be significantly improved because of the use of a single material. With the combined unique properties in this material, it has the great potential to enable wafer processes in different advanced packaging applications.