摘要
Naval Research Logistics (NRL)Volume 39, Issue 3 p. 369-388 Article Scheduling semiconductor test operations: Minimizing maximum lateness and number of tardy jobs on a single machine Reha Uzsoy, Reha Uzsoy School of Industrial Engineering, Purdue University, West Lafayette, Indiana 47907Search for more papers by this authorChung-Yee Lee, Chung-Yee Lee Department of Industrial and Systems Engineering, University of Florida, Gainesville, Florida 32611Search for more papers by this authorLouis A. Martin-Vega, Louis A. Martin-Vega Department of Industrial and Systems Engineering, University of Florida, Gainesville, Florida 32611Search for more papers by this author Reha Uzsoy, Reha Uzsoy School of Industrial Engineering, Purdue University, West Lafayette, Indiana 47907Search for more papers by this authorChung-Yee Lee, Chung-Yee Lee Department of Industrial and Systems Engineering, University of Florida, Gainesville, Florida 32611Search for more papers by this authorLouis A. Martin-Vega, Louis A. Martin-Vega Department of Industrial and Systems Engineering, University of Florida, Gainesville, Florida 32611Search for more papers by this author First published: April 1992 https://doi.org/10.1002/1520-6750(199204)39:3<369::AID-NAV3220390307>3.0.CO;2-FCitations: 49AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinkedInRedditWechat Abstract We examine a class of single-machine scheduling problems with sequence-dependent setup times that arise in the context of semiconductor test operations. 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