A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories

Power supply voltage reduction is a primary enabler for sustaining the increasing demand for ultra-low power processors. On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells are used instead. These bit-cells leak their data strongly in one direction, whereas the leakage in the opposite direction is considerably lower. Due to their intrinsic limited Data Retention Time (DRT), these memories require power-hungry refreshing, which degrades performance. In an attempt to extend the DRT of a bit-cell, theoretically to infinity, compounds of various types of storage nodes in a single bit-cell, storing the datum and its complement, were examined here. A rigorous proof shows that under realistic leakage models, there is an inherent incompleteness preventing the proper readout and decision of the stored value after a certain time. Adopting the idea of dual-polarity complementary storage nodes, a new eDRAM self-refreshable bit-cell is proposed that yields a considerably extended DRT. The dual-polarity property enables the refreshing of an entire memory array in a single clock cycle, thus almost nullifying the unavoidable performance loss occurred by row-by-row ordinary power-hungry refreshing.