Analysis and Suppression for Gate Oscillation Caused by Body Diodes on Paralleled SiC MOSFETs Application

Paralleled SiC MOSFETs are widely used in high-power applications to extend power range. However, the inconsistent body diodes of paralleled SiC MOSFETs can result in severe gate oscillation. This article analyzes the gate oscillation phenomenon resulting from inconsistent body diodes of paralleled SiC MOSFETs and develops two simplified oscillation network models, corresponding to different oscillation frequencies. The built models demonstrate remarkable accuracy, with errors of 2.6% at low frequency and 3.5% at high frequency. To efficiently suppress gate oscillation, four methods are proposed from the perspectives of stabilizing gate voltages and interrupting oscillation loops and are evaluated across five dimensions. Finally, a double pulse test platform with a highly symmetrical circuit is set up to validate the effectiveness of proposed methods in repressing gate oscillation, which provides design guidance for the application of paralleled SiC MOSFETs.