Influence of the SiC JFET Gate Impedance on the Off-State Voltage Balance in Cascode Configuration

SiC cascodes are an increasingly utilised circuit configuration. They have low on-state resistance and can switch fast, with good temperature insensitivity. The design of casco des involves determining the proper capacitance ratio between the SiC JFET and low voltage MOSFET. The designer should also implement a circuit/packaging design with appropriate JFET gate loop impedance to have a stable switching device that does not exceed the MOSFET blocking voltage during the repetitive OFF -state. An accurate model is presented, parameterised using the device datasheets, and involves all the parasitics of a SiC JFET cascode configuration. The model is accompanied by experimental measurements and is used to explore and explain the influence of the JFET gate loop impedance on the switching performance of the cascode and the OFF -state voltage of the MOSFET. The JFET gate resistance is found to be very influential in determining the repetitive LV MOSFET blocking voltage and the HV JFET OFF-state gate voltage.