Simulation Study of the Effect of Chip Warpage on the Bonding Process of Vertical Micro-LED Arrays

As an emerging display technology, Micro Light Emitting Diode (Micro-LED) faces challenges in terms of transfer yield and display uniformity, both of which are impacted by heterogeneous integration technology. The warpage phenomenon of Micro-LED chips directly affects the pressure distribution during the bonding process, resulting in a decrease in the bonding yield of some regions. In this study, the COMSOL Multiphysics finite element simulation software was used to delve into the impact of warpage on the bonding results. By proposing the method of adding a filling layer around metal bumps, the stress concentration caused by warping has been alleviated, thereby improving the overall bonding quality and interconnect strength. The research findings indicate that temperature is a crucial factor affecting chip stress during the bonding process. When the chip is not warped, the filler can significantly reduce bump stress and improve stress distribution. In the case of warping, although the filler does not significantly improve the stress of the bumps, it can effectively reduce the stress of adjacent bumps and improve the stress distribution. In addition, filler can also effectively inhibit the warpage of adjacent bumps.