CMOS芯片
逐次逼近ADC
Boosting(机器学习)
计算机科学
带宽(计算)
电子工程
电容器
采样(信号处理)
交错
电效率
功率(物理)
电气工程
物理
工程类
探测器
电压
电信
量子力学
机器学习
作者
Yan Zhu,Chi-Hang Chan,Zihao Zheng,Cheng Li,Jianyu Zhong,Rui P. Martins
出处
期刊:IEEE Transactions on Circuits and Systems I-regular Papers
[Institute of Electrical and Electronics Engineers]
日期:2018-11-01
卷期号:65 (11): 3606-3616
被引量:11
标识
DOI:10.1109/tcsi.2018.2859027
摘要
This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step.
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