The Pb(Zr0.2,Ti0.8)O3/ZnO/GaN Ferroelectric–Semiconductor Heterostructure: Insight into the Interfacial Energy Level Alignments

Abstract Ferroelectric/semiconductor heterostructures promise to be the backbone of next‐generation “green” data storage devices combining ultrashort switching times and ultralow switching power with a simplified device structure and low‐cost processing. One promising candidate to realize such resistive memory devices is the ferroelectric‐Pb(Zr0.2,Ti0.8)O3/semiconductor–ZnO/GaN heterostructure. A detailed knowledge about the energy level alignments in this heterostructure is of utmost importance to understand the charge carrier transport mechanism as that is what determines the macroscopic performance of corresponding ferroelectric/semiconductor‐based electronic devices. Employing hard X‐ray photoelectron spectroscopy, favorable type‐II energy level alignments at the Pb(Zr0.2,Ti0.8)O3/ZnO and ZnO/GaN interfaces are found with, however, significantly lower offsets in the valence as well as the conduction band for the latter. As a result, the formation of a high‐resistance state and a low‐resistance state can be explained by a combination of polarization effects and related changes in the energy level alignment. The charge carrier transport through the Pb(Zr0.2,Ti0.8)O3/ZnO/GaN heterostructure may in the low‐resistance state be limited by the significant hole barrier at the ZnO/GaN interface. The gained insight opens a new route for device optimization by deliberate interface engineering promising improved tunable resistive memory devices.