NMOS逻辑
PMOS逻辑
单层
材料科学
光电子学
逻辑门
MOSFET
纳米技术
晶体管
电气工程
工程类
电压
作者
Wouter Mortelmans,Pratyush Buragohain,Carly Rogan,A. Kitamura,C. J. Dorow,Kevin P. O’Brien,R. Ramamurthy,J. Lux,Tao Zhong,Shane Harlson,Elizabeth C. Gillispie,Timothy M. Wilson,A. Oni,Ashish Verma Penumatcha,Mahmut S. Kavrik,K. Maxey,Azimkhan Kozhakhmetov,Chou‐Ching K. Lin,S. Lee,A. Vyatskikh
出处
期刊:
日期:2024-06-16
卷期号:: 1-2
被引量:19
标识
DOI:10.1109/vlsitechnologyandcir46783.2024.10631395
摘要
2D transition metal dichalcogenides are promising candidates as channel material choice in ultimately scaled CMOS. We report record performance in GAA 2D NMOS transistors using monolayer MoS2 with three advances: scaled gate length (Lg) down to 25nm, scaled contact length (Lc) of 38nm, and the elimination of the low-k “inter-layer” in the gate stack enabling the first fully high-k GAA 2D device. We achieve 90% yield for scaled Lg <50nm with SS of 86mV/dec and on-currents reaching $485\mu \mathrm{A}/\mu \mathrm{m}$. Drive currents of 342μA/μm are maintained after contact length scaling down to $\sim 40\text{nm}$. We report the first BTI on any 2D GAA device and deposited high-k interface, showing $\text{HfO}_{2}$ may be advantageous for 2D reliability compared to typical $\text{Al}_{2}\mathrm{O}_{3}$ inter-layers. Signs of short-channel effects are observed at the shortest Lg, identifying EOT scaling as essential area of improvement. We also report record ION=92μA/μm in scaled Lg GAA PMOS transistors with monolayer WSe2.
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