Review of virtual wafer process modeling and metrology for advanced technology development

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development is a major contributor to time and cost overruns. The growing inability to characterize many of the subtle and complicated features and yield limiting factors of a given technology is another serious constraint. We demonstrate the use of process modeling, virtual wafer fabrication, and virtual metrology in process development of advanced logic and memory. Accurate and predictive process modeling, in combination with virtual metrology enables the characterization of any feature on any given structure, is becoming a key requirement in advanced technology development. Virtual fabrication also accelerates the semiconductor development cycle, by substituting limited and lengthy wafer-based experiments with fast, large-scale virtual design of experiment. Several applications of virtual process modeling and metrology are illustrated in 3D NAND, DRAM, and logic technology. These applications include studies of 3D NAND pillar etch alignment (including tilt, twist, and bowing), DRAM capacitor process window optimization, advanced FinFET logic pitch-walking, and BEOL performance optimization.