Exploration d'une architecture tuilée reconfigurable de mémoire calculante pour les applications gourmandes en données

Current computing architectures for data-intensive applications are facing severe memory access limitations.Power hungry caches are not efficient anymore, the memory available to the cores is more and more limited in both capacity and latency.Unfortunately, the trend in memory technologies does not scale as fast as the computing performances, leading to the so called memory wall.To address these challenges, the main directions followed in the research community are both at the architecture level and technology level: new architecture with computation immersed in memory, coupled to on-chip Non-Volatile Memory (NVM) for increased density, and advanced 3D architectures for increased memory capacity while offering more tightly coupled computing and memory.As a first step towards these directions, this PhD thesis addresses the architectural study of computation immersed in memory architecture with an increased memory sizing, scalability and reconfigurability using standard CMOS technologies.Recent techniques that bringing computing as close as possible to the memory array such as, In-Memory Computing (IMC), Near-Memory Computing (NMC), are expected to solve these limitations, but are facing limitations such as, fixed vector size and total available memory capacity.To process data-intensive applications with larger datasets, in this thesis, I propose a scalable and reconfigurable tile-based architecture composed of SRAM-based NMC tiles, each enabling arithmetic and logic operations within the memory.The combination of a horizontal scalability scheme and a vertical data communication offers an adaptive vector size for maximum performance onto the NMC tiles.In terms of programming model, this architecture can be programmed as an accelerator and executes vector-based kernels available on existing SIMD engines.For architecture exploration, performance and energy of data-intensive kernels are quantified using an instruction-accurate simulation platform using SystemC/TLM, calibrated on existing NMC SRAM tile designed in 22 nm FDSOI technology.Compared to 512-bit SIMD architecture, the proposed NMC architecture achieves an Energy-Delay Product (EDP) reduction up to 52x and 71x for linear and quadratic computational complexity kernels, respectively.