Design of Low Parasitic Inductance Three-level T-type SiC-MOS/Si-IGBT Module

In this paper, a low parasitic inductance three-level T-type SiC-MOS/Si-IGBT module for distributed photovoltaic application is designed. Analysis of the current commutation loops of this hybrid module is presented. To reduce parasitic inductance, a stacked substrates structure is used to form vertical power commutation loop. A stacked bond wire substrates structure is adopted. Finally, a hybrid module with stacked bond wire substrates structure is built and testing results are provided.