Area-Efficient Silicon Carbide SCR Device for On-Chip ESD Protection

This article introduces a silicon carbide (SiC)-based high-voltage silicon-controlled rectifier (HV-SCR) for on-chip electrostatic discharge (ESD) protection. The SiC HV-SCR is formed by implanting a $\text{p}^{+}$ region into the n-well of SiC laterally diffused metal-oxide semiconductor (LDMOS) structures. Both LDMOS and HV-SCR structures were characterized using a transmission line pulse (TLP) system to investigate their ESD behaviors. The TLP measurement results show that the trigger voltage ( ${V}_{\text {t1}}$ ) of the SiC HV-SCR is $\sim 230$ V and has minor dependence on the drift length. The ${V}_{\text {t1}}$ value of the SiC LDMOS decreases from 224 to 202 V when its drift length decreases from 6 to 4 $\mu \text{m}$ . TLP measurements with 500- $\Omega $ impedance were conducted to obtain an accurate holding voltage ( ${V}_{\text {h}}$ ) and failure current ( ${I}_{\text {t2}}$ ) of HV-SCR and LDMOS. Relatively high ${I}_{\text {t2}}$ (i.e., 33 mA/ $\mu \text{m}$ ) of the HV-SCR structure was observed, which is much stronger than the LDMOS structure (i.e., 0.2 mA/ $\mu \text{m}$ ). The ${V}_{\text {t1}}$ and ${V}_{\text {h}}$ values of HV-SCR were also investigated with varying gate bias voltages. Moreover, technology computer-aided design (TCAD) simulations of the SiC HV-SCR and LDMOS were carried out to further understand their ESD behaviors.