德拉姆
计算机科学
带宽(计算)
可测试性
嵌入式系统
堆积
可靠性(半导体)
电子工程
计算机体系结构
可靠性工程
工程类
计算机硬件
功率(物理)
电信
物理
量子力学
核磁共振
作者
Hong-Shin Jun,Jin-Hee Cho,Kangseol Lee,Hwa‐Young Son,Kwiwook Kim,Hanho Jin,Keith Kim
标识
DOI:10.1109/imw.2017.7939084
摘要
HBM (High Bandwidth Memory) is an emerging standard DRAM solution that can achieve breakthrough bandwidth of higher than 256GBps while reducing the power consumption as well. It has stacked DRAM architecture with core DRAM dies on top of a base logic die, based on the TSV and die stacking technologies. In this paper, the HBM architecture is introduced and a comparison of its generations is provided. Also, the packaging technology and challenges to address reliability, thermal dissipation capability, maximum allowable package sizes, and high throughput stacking solutions are described. Test technology and testability features are discussed for KGSD and 2.5D SiP.
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