Design of 6T, 5T and 4T SRAM cell on various performance metrics

As the technology is shrinking, a significant amount of attention is being paid on the design of high stability Static Random Access (SRAM) cells in terms of static Noise Margin (SNM) for different levels of cache memories. This paper presents a qualitative design of 6T, 5T and 4T Static Random Memory Access cell in terms of Read cell current, Write time, Static Noise Margin (Read and Hold), Write Noise Margin in 65nm CMOS technology. Simulation results shows that the 6T SRAM cell exhibits 173% higher SNM than 4T SRAM cell which indicates that it is highly stable than 4T configuration.