Logic Synthesis Optimization Sequence Tuning Using RL-Based LSTM and Graph Isomorphism Network

As a key step in the IC design flow, logic synthesis involves various logic optimization algorithms to be iteratively applied to the circuit. However, how these algorithms are used is usually determined by heuristics, and it does not always yield well optimizations on all circuits. To achieve well optimized results, engineers need to tune the sequence consisting of these logic optimization algorithms based on their knowledge. To overcome this limitation, in this brief, reinforcement learning (RL) proximal policy optimization (PPO) is proposed to train an agent to tune the optimization sequence. Specifically, graph isomorphic network with edge feature aggregation capability (GINE) is used to learn circuit representations and use circuit representations as state representations for the reinforcement learning agent. Furthermore, to enable the agent learning from historical operations, the Long Short-Term Memory (LSTM) is further embedded in reinforcement learning. The evaluation of the EPFL arithmetic benchmark shows that our model improves the area optimization under the delay constraint by 21.21% over existing methods.