芯片级封装
倒装芯片
包装工程
晶圆级封装
互连
扇出
模具(集成电路)
薄脆饼
造型(装饰)
炸薯条
包对包
集成电路封装
引线键合
材料科学
通过硅通孔
包装工业
电子包装
机械工程
计算机科学
电气工程
工程类
光电子学
纳米技术
电信
晶片切割
复合材料
胶粘剂
图层(电子)
出处
期刊:IEEE Transactions on Components, Packaging and Manufacturing Technology
[Institute of Electrical and Electronics Engineers]
日期:2022-01-18
卷期号:12 (2): 228-252
被引量:252
标识
DOI:10.1109/tcpmt.2022.3144461
摘要
In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.
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