Session 10 Overview: Continuous-Time ADCs and DACs

Continuous-time Δ Σ ADCs offer compact silicon area and low power consumption for various applications. The first two papers in this session present different techniques in continuous-time Δ Σ ADCs for audio applications and achieve impressive figures of merit. The third paper describes a new hybrid CT/DT loop architecture for a Δ Σ modulator without requiring any calibration or tuning. The fourth paper proposes a CT loop filter with DT noise shaping achieving $4^{{th }}$ -order noise shaping using a single OTA. The fifth paper introduces a pipelined ADC with a 1 ^st stage SAR and $2^{{nd }}$ stage $2 x$ -time-interleaved CT incremental Δ Σ ADC. The last two papers in this session describe techniques utilized to achieve high-linearity multi-GHz DACs. The sixth paper describes a 16GS/s DAC for software radio base stations. The last paper presents a 64GS/s DAC for BIST of RF sampling ADCs.